Deep silicon etching technology is the core process for achieving high aspect ratio three-dimensional structure processing in the semiconductor manufacturing field, widely used in the core structures of transistors, storage capacitors, and MEMS manufacturing. Its technical system is dominated by dry etching, which achieves high-precision anisotropic processing of silicon materials through the synergistic effect of plasma physical bombardment and chemical reactions. Among them, deep reactive ion etching (DRIE) technology has become a key solution for microstructure processing due to its ability to achieve aspect ratios of over 40:1 and 90 °± 1 ° sidewall perpendicularity. In terms of technical principles, mainstream DRIE processes are divided into two categories: Bosch processes and low-temperature processes.
The main application areas of deep silicon etching technology are:
1) MEMS devices: Deep silicon etching technology is the core process of MEMS device manufacturing, widely used in the deep groove, cavity, and cantilever structure processing of inertial sensors, pressure sensors, microactuators, and microfluidic chips. Its core requirements focus on mechanical structural stability and high anisotropy, requiring precise control of etching parameters to achieve high-precision forming of three-dimensional microstructures.
2) Semiconductor packaging: The core application of deep silicon etching technology in the field of semiconductor packaging is through silicon via (TSV) processing, which realizes chip interconnection through vertical conductive paths and supports advanced packaging technologies such as 3D IC stacking and heterogeneous integration. TSV etching needs to meet the dual requirements of high aspect ratio and interconnect reliability. The DRIE system, designed with low-frequency pulse bias, can effectively control the non bottom cutting effect of SOI wafers and meet the high-precision etching requirements of advanced packaging for multi-layer material systems.
3) 3D NAND storage: 3D NAND storage breaks through the storage density bottleneck by vertically stacking Si ∝ N ₄/SiO ₂ multilayer structures, and its manufacturing requires high-precision deep silicon etching processes to support the formation of complex three-dimensional structures. As the number of stacked layers increases to 128 and above, aspect ratio (HAR) becomes a core challenge, requiring etching processes to have extremely high verticality control (error<0.5 °) and global uniformity.
In terms of process innovation, the inductively coupled plasma (ICP) etching system meets the precision molding requirements of step structures, channel holes, and CMOS circuit connections through the coordinated control of high-density plasma (>10 ¹²/cm ³) and adjustable bias power supply.
4) Microfluidics and Optical Devices
The application of deep silicon etching technology in the fields of microfluidics and optical devices needs to meet the dual core requirements of fluid dynamics performance and optical transmission efficiency. The optimization of process parameters directly affects the stability of device functionality. In microfluidic devices, such as MEMS liquid chromatography microchips, fluid channel functionality is achieved by etching 30 μ m deep columnar structures, which require precise structural dimensions and uniform distribution to ensure fluid flow stability; MEMS optical chopper requires etching a 15 μ m thick silicon layer on the SOG substrate, requiring no notch sidewalls and high surface flatness to reduce light scattering.
In terms of material and process selection, SU-8 adhesive is commonly used as a mask in the field of biochips, while optical devices such as photonic crystals and waveguides tend to use quartz substrates. Cryogenic DRIE can reduce sidewall roughness and improve the performance of photonic devices. In practical applications, microfluidic devices require high etching rates and controllable scallop structures, while optical devices rely more on notch free sidewalls and nanoscale groove depth errors (<5 nm), both of which need to be achieved through mask design and process parameter optimization.

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