In the trend of semiconductor transistor size becoming smaller and chip functionality becoming increasingly complex, system level testing (SLT) has become crucial. System level testing (SLT) refers to testing a device under test (DUT) in a simulated terminal usage scenario, purely through operation and use, without the need to create test vectors like traditional automated test equipment (ATE). Testing still needs to be written, but in a different way.
System level testing is also known as functional testing. Due to the automation of structural testing, it can more effectively meet the requirements of fault coverage. Therefore, Automatic Test Program Generation (ATPG) has become the main source of test vectors.
ATPG and other structural technologies require manual structures such as scan chains to access the entire circuit, which results in most tests being completed in test mode. Although this is beneficial for testing, Design for Testability (DFT) and ATPG also have drawbacks, including:
The test mode masks faults that are only visible in functional mode
The ATPG test vector will not cover all parts of the circuit, such as the interface between IP blocks
The chip under test will not experience real operation during structural testing, and some edge faults and hysteresis faults cannot be detected, including noise in power and clock distribution circuits; The test vector causes the chip under test to heat up; ATPG does not cover complex real-world scenarios, and manually writing such test vectors may be very difficult or even impossible; The testing does not include system software.
By comparison, when using SLT, test engineers can use the chip under test as if it were in a real environment, thereby discovering faults that were previously undetected. Given that the initial defect rate increases upon entering testing and the allowed defect rate significantly decreases upon exiting testing, component manufacturers are more reliant on testing than ever before. The current technology has far exceeded the threshold of 1 billion transistors per chip. Although 99.5% fault coverage is still acceptable, if calculated based on 1 billion pieces, 0.5% is still a lot.
The electronic design automation (EDA) industry has made great efforts to achieve synchronous improvement of fault coverage and density, but the improvement of fault coverage has lagged behind due to the following reasons.
Fault mode: Whenever new innovative technologies are introduced in integrated circuit manufacturing, it also means the introduction of new fault modes. But the development of new testing techniques required to detect these fault modes is slow and always difficult to keep up with the pace. Through SLT, manufacturers can implement functional testing to trigger and capture real faults caused by new failure modes.
SoC internal interface: ATPG focuses on testing IP blocks and achieving very high fault coverage for these IP blocks. However, as SoCs become increasingly complex and more IP blocks are added, the interfaces between these IP blocks become more important components in the chip, leading to a decrease in overall fault coverage.
Another challenge with IP block interfaces is that they are typically asynchronous, which makes testing more difficult. In addition to testing the complexity of asynchronous interfaces, scanning all possible timing combinations is also very time-consuming.
The EDA industry provides tools to drive SoC system validation, but it is not yet clear how these simulations will be ported to ATE, or even if they can be ported to ATE. SLT supports testing of interfaces, as the tested chip will be used in a real environment to detect faults that may not have occurred in ATE.
The increasing complexity of SoC and SIP, coupled with the increasingly stringent quality requirements of end users, is driving this trend, SLT has been widely adopted and has become a key component of the testing strategy for chips under test. By using SLT to perform functional testing on the test chip in a simulated terminal environment, equipment manufacturers can prevent missed detection faults that are difficult to detect using traditional wafer and packaging testing techniques.
In addition, by adding the SLT stage to the testing process, not only can missed faults be captured, but testing can also be moved between platforms, including running low yield tests in the early stages of the testing process and running high yield tests in the SLT testing equipment in the later stages. This will help customers achieve the ideal testing cost/quality ratio.

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