1. Function design stage: design the application of the target product, set some indicators such as function, performance, interface specification, temperature, power consumption, etc. as the input basis for subsequent circuit design. According to the needs of the market and the company, complete the detailed definition of the overall structure, specification parameters, module division, use technology and various functional modules of the chip. After the overall design planning is completed, the design scheme of each dimension will be formulated. The chip design scheme decomposes the design modules step by step in a top-down manner to form the design scheme of each module.

2. Design description and behavior level verification: According to the overall design requirements of the chip, the SoC can be divided into several functional modules, and whether these functional modules need to use IP cores can be determined. This process directly affects the internal architecture of SoC and the top-level signal interconnection of each module, and plays a decisive role in the subsequent design process. Therefore, products and IP cores need to be carefully selected. For modules that do not need IP cores, VHDL/Verilog and other hardware description languages can be used to complete the design of each module of the hardware circuit. At the same time, the function points of each module are defined, and the function simulation verification and behavior level verification are performed according to the function points. The behavior level simulation verification does not consider the timing delay, so it cannot cover the timing related problems, and can only ensure the functional correctness of the design. The correctness of timing delay needs to be realized by other means.

3. Logic synthesis: After the design description is determined, the code can be synthesized using logic synthesis tools. The synthesis process needs to select the appropriate logic device library and SDC timing constraint file as the synthesis parameters of the synthesis logic circuit. The designer needs to determine the correctness of the SDC constraint file. If it is an IP core, the IP nuclear factory will provide the original SDC constraint file, but it is not suitable for the overall SDC constraint of the chip. Therefore, no matter the IP core used or the verilog code written, SDC constraint files need to be compiled. At the same time, SDC constraint file is also one of the input files for CDC/RDC code rule check.

4. Layout and post-simulation: Layout refers to the reasonable arrangement of the designed functional modules on the chip and the planning of their positions. Wiring refers to the completion of interconnection and wiring between various modules. Post-simulation is the simulation with SDF delay parameters. Post-simulation is used to test whether the timing of the chip meets the requirements. Functional simulation has been verified during the pre-simulation. Therefore, post-simulation focuses more on the setup and hold time during the simulation process. For problems in post-simulation, it is necessary to locate the problem point and determine whether back-end repair, ECO repair or RTL re-integration is required.

SOC design process, including the whole process of digital circuit design front-end and back-end. Specific parts include:

——Hardware Design Specification

——Module Design&IP Reuse

——Top Level Integration

——Pre-layout Simulation

——Logic Synthesis

——Floorplan

——Power Analysis

——Placement&Optimization

——Static Timing Analysis (STA)

——Formal Verification

——DFT, Design for Test

——Clock Tree Synthesis

——Routing

——Parasitic Extraction

——Post-layout Simulation

——ECO, Engineering Change Order

——Physical Verification