Chip testing is an important link to ensure product yield and cost control. Its main purpose is to ensure that the chip can fully realize the functions and performance indicators specified in the design specification in harsh environments, so as to judge whether the chip performance meets the standards and whether it can enter the market.

As the product enters the era of high-performance CPU, GPU, NPU, DSP and SoC, more and more modules are integrated in the chip, and the failure modes in the manufacturing process are also increased accordingly. The importance of chip testing is highlighted. The existing integrated structure, which is mainly packaging and supplemented by testing, can no longer meet the test requirements, and the trend of separation of packaging and testing is gradually increasing.

The importance of testing is highlighted, and the separation of sealed testing is the general trend

Chip testing is mainly divided into three stages: design verification in chip design, wafer testing in wafer manufacturing (CP testing), and finished product testing after packaging (FT testing). CP testing and FT testing are the core links of semiconductor post test.

1. Design verification

Design verification is to use the corresponding verification language, verification tools and verification methods to verify whether the chip design meets the requirements and specifications defined by the chip, whether the risks have been fully released, and whether all defects have been found and corrected before chip production.

It is well known that the cost of the chip is very high. In the chip production process, the chip alone accounts for 60% of the total cost. Take 28nm chip as an example: according to Gartner's data, the average design cost of 28nm chip is 30 million dollars. After the chip is streamed, it is found that the design fault can hardly be changed, so the chip design verification is the optimal solution to reduce the loss of the chip.

2. CP test and FT test

CP test is located between wafer manufacturing and packaging during the whole chip manufacturing process. By installing a probe made of gold wire as fine as hair on the detection head and contacting the pad on the grain, its electrical characteristics are tested. Unqualified grains will be marked, and then when the wafer is cut into independent grains by grains, the unqualified grains marked will be eliminated.

FT test is the final function and performance test of the chip after the completion of packaging, and is the final link of product quality control. Generally speaking, there are more and more CP test items, and fewer FT test items, but they are all key items with strict conditions.

The duration of CP test and FT test is directly related to the test coverage. The longer the test time, the better the test coverage. However, the charging standard is also based on the test time. The more test items, the longer the test time and the higher the cost.

The test cost in the chip manufacturing process accounts for about 5% of the design cost. In order to save cost, some companies cut and package directly after the completion of the chip, cutting off the CP test link and only doing a small amount of package test (FT test). However, the result of this is that some defective chips can not be detected and directly installed to customers. If the chip with functional defects is sold to customers, the loss will be extremely heavy, not only economic compensation, but also damage the reputation. It is of great significance for customer return, and its value is immeasurable.

It can be seen that testing is no longer a supporting role of chip manufacturing, nor an accessory of packaging. Chip testing is very necessary and must be focused on. However, in recent years, the chip testing industry has been forced to bundle with packaging for a long time, which leads to the lack of ability to undertake customers. In addition, the whole industry has started slowly, so it faces many difficulties in the entire development process.

Problems to be overcome in chip testing

1. Chip testing is becoming more and more expensive.

2. New materials are uncontrollable.

Semiconductor materials are the most important link in the upstream of the industrial chain, which can affect every production link in the downstream. More and more new materials are added to chips, bringing many problems to chip testing. These materials are soft or brittle, or used to make thin films or increase electron mobility, which require more characterization before testing, and may even be damaged during processing or testing. These problems require a lot of time and effort to solve.

3. High standard testing requirements.

In the past two years, automatic driving vehicles or industrial applications have made continuous progress, and testing needs to be more rigorous. Especially in the automobile industry, which has a high standard for safety, components with poor performance are not allowed anywhere in the supply chain. Automobile manufacturers require parts to be free of defects for up to 17 years. Developing devices with this defect level requires more extensive testing, deriving the demand for more precise testing equipment, and testing costs will naturally rise.

4. The evolution of encapsulation technology.

The rebirth of 3D packaging technology is called the continuation of Moore's Law. Similarly, the defects of any chip in the package are difficult to detect and expensive, such as a single 3D chip. It needs to track signals passing through two or more chips, and testers cannot directly access certain layers. To solve these problems, it must be costly.

5. The self-sufficiency rate of equipment is low and the cost is high.

IC testing equipment mainly includes testing machine, sorter and probe bench. The domestic market share is extremely low. In addition to the fact that the testing equipment is mainly imported, the single machine value is as high as $300000 to $1 million. The heavy asset industry has obvious characteristics and huge capital investment. In the past, many companies invested in their own equipment to test their products, but the equipment change needs to be consistent with the evolution of chip technology. Considering the high cost, except Fabless, the original IDM, wafer manufacturing and packaging plants tend to hand over the testing part to third-party testing enterprises for cost reasons. With the development of third-party testing companies becoming more and more mature, the diversified accelerated testing schemes of testing products are rapidly iterative, and the endless orders can also ensure the capacity utilization.

In fact, to enter mass production, a chip not only needs to go through a set of very strict verification and testing processes, such as characteristic test and reliability test, but also needs to prepare a series of efficient and reliable test plans. This series of test plans must be able to reliably separate good products from bad products, and provide accurate measurement data to provide valuable information for reliability testing; At the same time, accurate and reliable data must be provided for designers in the characteristic verification test; Finally, we must separate the good products reliably in mass production with high efficiency and low cost.

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