On the real production line, there is a very realistic and cruel hurdle: before the chip is cut or packaged, it must first undergo electrical testing on the entire wafer. This step is commonly referred to as CP (Chip Probing), also commonly known as Wafer Sort or Wafer Test.  
The CP testing site usually consists of three types of core equipment: ATE (Automated Test Equipment), Probe (Wafer Probe), and Probe Card.
ATE is responsible for applying voltage, current, clock, digital excitation, RF signals, and collecting and returning results;
The probe station is responsible for accurately moving the wafer to the testing position, aligning each die with the probe in sequence;
The probe card is like a "mini bridge" that connects the ATE test channel to the chip's pads or bumps.
During testing, the needle tip on the probe card will be slightly pressed down, forming a reliable contact with the wafer surface. This action is called Touchdown. On the production line, CP testing is not just testing one chip, but scanning the entire wafer one by one according to the testing procedure. The results of each Die will be recorded to form a Wafer Map. The wafer diagram will indicate the coordinates of each Die, pass/fail results, failed items, bin numbers, key electrical parameters, etc. The subsequent cutting and packaging processes rely on this diagram to determine which dies are picked up and which dies are skipped. What are the main steps of CP testing?
Short circuit test: The CP test is the first step and the most basic connection check. The most typical project is OS (Open/Short), also known as Continuity Test or Contact Test. ATE applies a small current to a pin through PMU (Parametric Measurement Unit) or PPMU (Per Pin Parametric Measurement Unit), and then measures the voltage response. If this step is not successful, it is meaningless to test any more advanced parameters in the future.
DC parameter test: After passing the short-circuit test, the CP test will enter the DC (Direct Current) parameter test. DC parameters measure the basic electrical performance of a chip under static or quasi-static conditions. For digital ICs (Integrated Circuits), common DC parameters include input level, output level, input leakage, output driving capability, and power supply current. One of the most critical types is power consumption and leakage testing.
Functional testing: For digital chips, ATE will input a test vector to DUT (Device Under Test), which is a set of designed 0/1 excitations, and then compare the chip output to see if it meets expectations. Simple chips can directly generate test vectors based on the truth table; Complex SoC (System on Chip) often relies on DFT (Design for Testability) structure. Typical DFT techniques include Scan Test, ATPG (Automatic Test Pattern Generation), LBIST (Logic Built In Self Test), MBIST (Memory Built In Self Test), and JTAG (Joint Test Action Group, also commonly referred to as Boundary Scan Interface). The purpose of these mechanisms is to enable testing equipment to more easily control internal nodes of the chip, observe internal states, and thus improve fault coverage.
AC parameter testing: For digital chips, AC testing checks Propagation Delay, Rise Time, Fall Time, Setup Time, Hold Time, Pulse Width, and Fmax (Maximum Operating Frequency). These projects determine whether the chip can operate stably at the target frequency. Die on the same wafer may not have completely consistent performance due to local process fluctuations, differences between the center and edges of the wafer, transistor threshold shifts, and changes in interconnect resistance. The testing program will divide them into different bins based on indicators such as speed, voltage, and power consumption.
After the CP test is completed, each Die will receive a result. The most intuitive ones are Pass Die and Fail Die, but in real production, they are usually finer and have multiple bins. These Bin information will be summarized in the Wafer Map. Engineers can observe the failure distribution through wafer diagrams. CP testing is not only a "quality inspection", but also a process feedback system. Future CP testing will not just be about measuring voltage and current with probes, but will increasingly resemble a data-driven quality decision-making system. It connects design, manufacturing, packaging, testing, yield, reliability, and supply chain, and is the most easily overlooked but extremely critical link in semiconductor manufacturing.

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