With the rapid development of the IC industry, the complexity of ICs and the performance of their electrical parameters are also increasing, which has brought many challenges to IC testing. Among them, the accuracy and stability of testing have always been the two major problems that plague engineers, especially in mass production ATE testing. So, how to achieve accurate and stable testing of various performance parameters of these ICs in testing to ensure product quality and avoid wasting a lot of testing time due to repeated retesting caused by unstable testing?
In IC testing, voltage testing is the most common parameter among all testing parameters, especially in the testing of analog chips, where voltage testing is more common and important. In debugging, it is also common to encounter inaccurate or unstable voltage measurements. For the problem of inaccurate testing, the correlation method is currently mainly used to adjust the testing error. However, this method can still be used for linear chips, but it is useless for nonlinear chips. For the problem of unstable testing, the method of taking the average of multiple measurements is mostly used to solve it. However, this approach only treats the symptoms rather than the root cause, and it can also bring hidden dangers to the quality of the product. So how to solve these problems in voltage testing?
Before developing a testing program, it is generally necessary to understand the functions and performance parameters of the chip being tested, so that you can have a clear understanding when developing and debugging the program. For example, when testing the output voltage parameters of an LDO, you must be clear about how long it takes for the output voltage to reach stability after adding the input voltage under the current input and output filtering capacitors. The waiting time you set in the program must be greater than this stability time in order to achieve accurate and stable testing. Of course, the output stability time of LDO is generally in the microsecond range (tens to hundreds of microseconds), so we are not likely to encounter such problems during debugging. However, sometimes we need to test the reference voltage inside the chip, but we cannot directly test it, and can only indirectly test it through other pins.
We test some static DC parameters during ATE testing, such as the voltage values at the bypass, Vo1, and Vo2 terminals. When you carefully read the manual of this chip, you will find that when the power supply voltage is 5V and the Cbypass is 1Uf (note that different power supply voltages and Cbypass capacitors have different stabilization times), the voltage at the bypass terminal needs at least 100ms to reach stability, and the voltage at the Vo1 and Vo2 terminals is also affected by the bypass terminal voltage. Therefore, in order to test these DC parameters stably and accurately, it is necessary to wait for more than 100ms after the chip is powered on before testing (it is necessary to consider the differences between different batches of chips, so the waiting time in actual testing). It can take around 120ms, but for mass production testing, the length of testing time will directly affect testing efficiency and testing costs. We must shorten the testing time! So how can we solve this problem? Generally, we can adopt the following two methods:
Firstly, the capacitance of Cbypass can be reduced, so that with the same charging current and voltage, the charging time will decrease as the capacitance decreases. A capacitance of 0.1uF or smaller can be used as a substitute, but this will definitely affect the testing of AC parameters (such as THD) later on, which needs to be solved through testing evaluation or the addition of relays.
Secondly, pre charging can be used to pre charge Cbypass with high current. If the bypass terminal is normally around 2.5V when the power supply voltage is 5V, we can pre charge it to 2.3V, which can also save a lot of time. However, we must be careful not to cause additional interference to the bypass terminal while charging, which may cause the chip to malfunction.
Vibration is also a common phenomenon during chip debugging, which brings many problems to chip testing. There are many reasons for vibration, such as the size of the output capacitive load, impedance mismatch, and improper feedback loop. However, we may not have noticed this during actual debugging. If the selected output capacitor is not within the required capacitance range for chip stability, the output will oscillate, resulting in inaccurate and unstable output testing. In addition, oscillations may occur not only during normal chip operation, but also during static conditions. Especially when testing operational amplifiers with high amplification, special attention should be paid to the input pins, and if necessary, isolation should be carried out to avoid introducing unnecessary noise and causing output oscillations.

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