The progress of semiconductor technology has promoted the development and application of power electronic devices, and has also led to the continuous reduction of chip size, promoting the development and progress of packaging technology, resulting in diversified packaging forms. The current design and development of power devices have the characteristics of low inductance, high heat dissipation, and high insulation capacity. Device packaging shows a trend of modularization, multifunctional, and compact volume. In order to achieve low inductance design of packaged devices, the device packaging structure is more compact, while the chip voltage level and power density of the packaging module continue to increase, posing challenges to packaging insulation and device heat dissipation. On the other hand, the reduction of chip size also increases the heat dissipation resistance of the chip, reduces the heat capacity, and increases the junction temperature of the chip, causing more significant temperature fluctuations, which affects the reliability of the power module.

As a core component of power electronic systems, power semiconductors have been widely used in fields such as life, transportation, power, industrial control, aerospace, and naval vessels. Power devices are showing the development characteristics of high frequency, high voltage, high power, and high temperature. At the same time, these features also pose great challenges to power device packaging, requiring consideration of the feasibility and adaptability of packaging structure, packaging materials, and packaging processes. If these cannot be effectively addressed, they will have a significant impact on the thermal, electrical, mechanical properties, and reliability of the device, and even lead to device failure.

Especially in the current development context of high voltage, high current, and compact packaging volume of power devices, the heat dissipation problem of packaged devices has become particularly prominent and challenging. The heat generated by chips can affect carrier mobility and reduce device performance. In addition, high temperature will also increase the thermal stress caused by the mismatch of coefficient of thermal expansion between different packaging materials, which will seriously reduce the reliability and working life of devices. Too high junction temperature will lead to catastrophic failure of devices and failure problems caused by thermal fatigue and high temperature acceleration of packaging materials leading to material degradation. Therefore, in a very limited packaging space, timely and efficient discharge of the chip's heat dissipation into the external environment to reduce the chip junction temperature and the temperature of various packaging materials inside the device has become an important issue that needs to be considered in the future power device packaging design process. With the increasing scale of the power grid and voltage levels, the power system is developing towards a more intelligent direction. High voltage, high-power, and high switching speed require power devices to undertake more diverse functions, and the working environment is becoming more harsh. In this context, in addition to the chip itself requiring high processing capacity, device packaging structure has become the key to limiting the overall performance of the device. However, traditional packaging is either limited by material properties or cannot adapt to the high temperature and heat dissipation requirements brought about by high-voltage, high current, and high switching speed applications due to its own structural design. To ensure the safe and stable operation of devices under high voltage and high power conditions, the development of new power devices with compact structure, simple design, and efficient heat dissipation has become an inevitable requirement for the development of power devices in future power systems.

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