The semiconductor production process consists of wafer manufacturing, wafer testing, chip packaging and post packaging testing, and the testing links mainly focus on WAT, CP and FT.

WAT (Wafer Acceptance Test) test, also known as PCM (Process Control Monitoring), is used to test the test key of Wafer Scribe Line, and to monitor whether each process is normal and stable through electrical parameters, such as CMOS capacitance, resistance, contact, metal line, etc. It is generally the basis for Wafer to ship from Fab factory to the seal testing factory before the completion of the manufacturing process by Wafer, The test method is to tie the Probe Card to the Metal Pad of the Test Key, and connect the other end of the Probe Card to the WAT test bench. The WAT Recipe automatically controls the test location and content. After testing a Test Key, the Probe Card will automatically move to the next Test Key until the whole Wafer is tested. There is a problem in the WAT test. If it exceeds the SPEC, it generally corresponds to the manufacturing process or machine shift of each module of the Fab, for example, the Litho OVL is abnormal, the ETCH CD is small, and the PVD TK is large. Wafer with serious WAT problems will be scrapped directly.

CP (Circuit Probing), also known as "Wafer Probe" or "Die Sort", tests the basic device parameters of each Die of the whole Wafer, such as Vt (threshold voltage), Rdson (on resistance), BVdss (source drain breakdown voltage), Igss (gate source leakage current), Idss (drain source leakage current), etc. Pick out the bad Dies, and mark them with ink dots (Ink), which can reduce the cost of packaging and testing. CP pass will be packaged only, Generally, the voltage and power of the test bench are not high. CP tests Wafer Die to check the process level of Fab factory.

CP test program and test method optimization is the direction of the Test Engineer's efforts. Here are some methods to reduce CP test costs.

1. The same Probe Card can test multiple Dies at the same time. How can you arrange them to reduce the test time? Assuming that the Probe Card can measure 6 Dies at the same time, it is 2 × 3 arrangement or 3 × 2, or 1 × 6. It will affect the number of times of needling, and different needle directions will also cause the problem of test time.

2. With the increasing size of the wafer and the increasing number of Die on the wafer, CP Test of many companies will adopt the Sampling test method to reduce the Test time. As for how to sample, different Test Recipe are involved. Some big data real-time monitoring software can control the needle direction according to a certain algorithm at the same time of testing. For example, when a Die fails, the Probe Card will automatically Test around the Die, Until there is no problem in the test, carry out the sampling test of the next Die. This method can significantly shorten the test time.

FT (final test) is to test the packaged Chip in terms of device application, and pick out the bad chip. After FT pass, process qual and product qual will be performed. FT is to test the package to check the packaging manufacturer's process level. The yield of FT is generally good. However, because FT tests contain more items than CPs, the Low Yield problem is also encountered. This situation is complex, and it is generally difficult to find the root cause. In a broad sense, FT is also called ATE (Automatic Test Equipment). Generally, after ATE is passed, it can be shipped to customers. However, for companies or products with high requirements, after FT is passed, there is SLT (System Level Test), also called Bench Test. The SLT test is more strict than the ATE test, which is generally a function test to test whether the function of specific modules is normal.

The ThermoTST TS-780 high and low temperature impact airflow meter of Chengdu Intercooling&Low Temperature Co., Ltd. takes speed, accuracy and reliability as the basic design standards, providing a very advanced temperature testing capability. The temperature conversion is from - 55 ℃ to+125 ℃ for about 10 seconds, with a wider temperature range of - 80 ℃ to+225 ℃; Through long-term multi working condition verification, it meets the requirements of more production environment and engineering environment. TS-780 is used to provide reliability tests such as aging test, characteristic analysis, high and low temperature temperature change test, temperature shock test, failure analysis, etc., as well as cold and hot tests of electronic components/modules such as chips, microelectronic devices, integrated circuits (SOC, FPGA, PLD, MCU, ADC/DAC, DSP, etc.), flash memory Flash, UFS, eMMC, PCBs, MCMs, MEMS, IGBT, sensors, small module components, etc.

WAT is a test conducted during wafer manufacturing. It monitors the stability of Fab manufacturing process by testing the electrical performance of the Scribe Line Test Key between Die and Die; CP test is an electrical test conducted after manufacturing and before sealing test to mark the bad Die and reduce the cost of packaging; FT is the functional test of the device after Die cutting, polishing and packaging, which can evaluate the packaging level of the packaging test factory. Only after all the tests are passed, can it be applied to the product.