In the past decade, the world we live in has become more reliant on electronic devices. This is particularly evident in cars: semi autonomous vehicle have been launched, and electronic devices or software can sense events and respond to events through automatic steering or braking. The high demand for device quality drives manufacturers to conduct comprehensive testing of their chips and systems to reduce the likelihood of end users encountering problems after purchasing.
In today's fiercely competitive market, component suppliers are constantly pushing the limits of technology to improve performance, battery life, and yield. This means that suppliers need to: ship at the new process node as early as possible, while the defect rate of the process may still be relatively high; Run at low voltage as much as possible to extend battery life; Fine tune PLL settings to maximize yield; Switch to using more advanced packaging technologies to improve density and performance. These requirements require extensive testing to ensure that high-quality components are used in the finished product. Therefore, as technology continues to push to its limits, the use of SLT can prevent missed faults and ensure that finished components meet the required high-quality standards.
Given that the initial defect rate increases upon entering testing and the allowed defect rate significantly decreases upon exiting testing, component manufacturers are more reliant on testing than ever before. The current technology has far exceeded the threshold of 1 billion transistors per chip. Although 99.5% fault coverage is still acceptable, if calculated based on 1 billion pieces, 0.5% is still a lot. The electronic design automation (EDA) industry has made great efforts to achieve synchronous improvement of fault coverage and density, but the improvement of fault coverage has lagged behind.
ATPG focuses on testing IP blocks and achieving very high fault coverage for these IP blocks. However, as SoCs become increasingly complex and more IP blocks are added, the interfaces between these IP blocks become more important components in the chip, leading to a decrease in overall fault coverage. Another challenge with IP block interfaces is that they are typically asynchronous, which makes testing more difficult. In addition to testing the complexity of asynchronous interfaces, scanning all possible timing combinations is also very time-consuming.
SLT supports testing of interfaces, as the tested chip will be used in a real environment to detect faults that may not have occurred in ATE.
Today's systems are very complex, so defects are difficult to avoid. The design verification phase should detect these defects before the parts or systems are put into production, but some of these design defects are difficult to detect, which leads to many systems needing to run for a long time to experience this form of system failure. More often than not, the number of hardware instances required to discover these defects is unrealistically large. As an alternative, running SLT in pre production and early production can provide a large number of test chips required to cause these rare faults, in order to repair hardware or software defects before delivering the product to end customers.
The increasing complexity of SoC and SIP, coupled with the increasingly stringent quality requirements of end users, has led to the wider adoption of SLT, which has become a key component of the chip testing strategy under test. By using SLT to perform functional testing on the test chip in a simulated terminal environment, equipment manufacturers can prevent missed detection faults that are difficult to detect using traditional wafer and packaging testing techniques. The demand for SLT in the market is constantly growing, and many companies hope to improve quality costs by implementing SLT.

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