Regarding the packaging structure of power devices, domestic and foreign research institutions and enterprises have conducted extensive theoretical research and development practices in structural design. Multiple structural packaging design concepts have been proposed and studied by domestic and foreign research institutions, and some structural design schemes have been successfully applied to commercial power devices.

The inherent properties of power devices and their special service environment determine that the internal packaging of devices is always subject to a comprehensive effect of multiple field effects such as electric field, heat, and stress coupling. The structural design of power devices should first meet the electrical insulation requirements, and on this basis, take into account the impact of structural design on other aspects such as packaging heat dissipation, stress between chips and packaging components. From the perspective of device heat dissipation, the packaging structure design should follow the principles of low thermal resistance in the heat dissipation path, as many heat dissipation paths as possible, and the maximum contact area on the heat transfer path. This requires consideration of the selection of packaging materials, the design of heat dissipation paths, and the area of contact interfaces between various components on the heat dissipation path at the beginning of design. But these inevitably increase the difficulty of packaging design and process implementation, and the packaging practice of a power device often involves considering a compromise of multiple factors. From the current research and development status of power devices both domestically and internationally, the packaging features of high temperature resistance, multiple heat dissipation paths, and large area connections are the development trend of future power device packaging, and also the inevitable choice to meet the performance requirements of future high-voltage and high-power devices.

At present, the maximum junction temperature of traditional Si based chips does not exceed 175 ℃, and the maximum range of temperature cycling does not exceed 200 ℃. Compared to Si devices, SiC devices have significant advantages in conduction loss, switching frequency, and high-temperature operation ability, with a maximum theoretical operating junction temperature of up to 600 ℃. The higher switching frequency of SiC wide bandgap semiconductor power devices can reduce the weight of passive devices and occupy smaller packaging volume, thus improving the power density of power devices. At the same time, SiC devices have higher thermal conductivity, which can more efficiently dissipate heat and energy from the chip. From the perspective of the heat dissipation path of the device packaging structure, power devices can be divided into the following:

(1) Single sided heat dissipation of packaging structure: single sided heat dissipation of bonding wire type, single sided heat dissipation of non bonding wire type

(2) Packaging structure double-sided heat dissipation: single substrate double-sided heat dissipation, double substrate double-sided heat dissipation, and no substrate double-sided heat dissipation

(3) Structural multi sided heat dissipation

At present, there is relatively little research and development on multi sided heat dissipation packaging devices. The high-voltage aspect is only limited to diodes, and there have been packaging attempts for SiC MOSFETs in the low-voltage aspect. The packaging of power devices ultimately presents a synthesis of multiple factors. While expanding the heat dissipation path, it is crucial to meet the insulation requirements of the packaging. Facing the development trend of high voltage and high power devices, high insulation and high heat dissipation capacity are the primary factors that need to be considered in future device packaging.

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